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PRELIMINARY
VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER
ICS813322-02
GENERAL DESCRIPTION
The ICS813322-02 is a member of the IC S HiperClockSTM family of high performance clock HiPerClockSTM solutions from IDT. The ICS813322-02 is a PLL based synchronous multiplier that is optimized for Ethernet or SONET-to-SONET clock jitter attenuation and frequency translation. The device contains two internal frequency multiplication stages that are cascaded in series. The first stage is a VCXO PLL that is optimized to provide reference clock jitter attenuation. The second stage is a FemtoClockTM frequency multiplier that provides the low jitter, high frequency SONET output clock that meets up to SONET OC-48 jitter requirements. Pre-divider and output divider multiplication ratios are selected using device selection control pins. The multiplication ratios are optimized to support most common clock rates used in Ether net and SONET applications. The VCXO requires the use of an external, inexpensive pullable crystal. The VCXO uses external passive loop filter components which allows configuration of the PLL loop bandwidth and damping characteristics. The device is packaged in a space-saving 32-VFQFN package.
FEATURES
* Two differential LVPECL outputs Each output supports independent frequency selection at 19.44MHz, 77.76MHz, 155.52MHz and 622.08MHz * Two differential inputs support the following input types: LVPECL, LVDS, HCSL * Accepts input frequencies from 8kHz to 156.25MHz including 8kHz,19.44MHz, 25MHz, 62.5MHZ, 77.76MHz, 125MHz, 155.52MHz and 156.25MHz * Each output has independently controlled dividers for common SONET clock rates * Attenuates the phase jitter of the input clock by using a lowcost pullable funamental mode VCXO crystal * VCXO PLL bandwidth can be optimized for jitter attenuation and reference tracking using external loop filter connection * FemtoClock frequency multiplier provides low jitter, high frequency output * Absolute pull range: 50ppm * FemtoClock VCO frequency: 622.08MHz * RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal (12kHz - 20MHz): 1.16ps (typical) * 3.3V supply voltage * 0C to 70C ambient operating temperature
nCLK1
PIN ASSIGNMENT
XTAL_OUT XTAL_IN nCLK0 CLK0 CLK1 VCCX VCC
* Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
32 31 30 29 28 27 26 25 LF1 LF0 ISET VEE CLK_SEL VCC nc VEE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
ODBSEL_1 ODBSEL_0 VCC ODASEL_1 PDSEL_2 PDSEL_1 PDSEL_0 VCCA
24 23 22 21 20 19 18 17
VEE nQB QB VCCO nQA QA VEE ODASEL_0
ICS813322-02
32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
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PRELIMINARY
BLOCK DIAGRAM
Loop Filter
XTAL_IN ISET
LF0
LF1
PDSEL_[2:0] Pullup
3
XTAL_OUT
Output Divider
QA
VCXO Input Pre-Divider
CLK0 nCLK0
19.44MHz
0
CLK1 nCLK1 CLK_SEL Pulldown
1
000 = 4 001 = 9720 010 = 12500 011 = 31250 100 = 38880 101 = 62500 110 = 77760 111 = 78125
Phase Detector
00 = 32 01 = 8 10 = 4 11 = 1
2
nQA
VCXO
Charge Pump
FemtoClock PLL 622.08MHz
Output Divider
ODASEL_[1:0]
VCXO Feedback Divider /9720
QB
VCXO Jitter Attenuation PLL
00 = 32 01 = 8 10 = 4 11 = 1
2
nQB
ODBSEL_[1:0]
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PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3 4, 8, 18, 24 5 6, 12, 27 7, 20, 23 9, 1 0, 11 13 14, 15 16, 17 19, 20 21 22, 23 25 26 28 29 30, 31 32 Name LF1, LF0 ISET V EE CLK_SEL VCC nc PDSEL_2, PDSEL_1, PDSEL_0 VCCA ODBSEL_1, ODBSEL_0 ODASEL_1, ODASEL_0 QA, nQA VCCO QB, nQB nCLK1 CLK1 nCLK0 CLK0 XTAL_OUT, XTAL_IN VCCX Type Analog Input/Output Analog Input/Output Power Input Power Unused Input Power Input Input Output Power Output Input Input Input Input Input Power Pullup/ Pulldown Pulldown Pullup/ Pulldown Pulldown Pulldown Pullup Description Loop filter connection node pins. Charge pump current setting pin. Negative supply pins. Input clock select. When HIGH selects CLK1/nCLK1. Pulldown When LOW, selects CLK0/nCLK0. LVCMOS/LVTTL interface levels. Core power supply pins. No connect. Pre-divider select pins. LVCMOS/LVTTL interface levels. See Table 3A. Analog supply pin. Frequency select pins for Bank B output. See Table 3B. LVCMOS/LVTTL interface levels. Frequency select pins for Bank A output. See Table 3B. Pulldown LVCMOS/LVTTL interface levels. Bank A differential clock outputs. LVPECL interface levels. Output power supply pin. Bank B differential clock outputs. LVPECL interface levels. Inver ting differential clock input. VDD/2 bias voltage when left floating. Non-inver ting differential clock input. Inver ting differential clock input. VDD/2 bias voltage when left floating. Non-inver ting differential clock input. Cr ystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Power supply pin for VCXO charge pump.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
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TABLE 3A. PRE-DIVIDER FUNCTION TABLE
Inputs PDSEL_2 0 0 0 0 1 1 1 1 PDSEL_1 0 0 1 1 0 0 1 1 PDSEL_0 0 1 0 1 0 1 0 1 Pre-Divider Value 4 9720 12500 31250 38880 62500 77760 78125 (default)
TABLE 3B. OUTPUT DIVIDER FUNCTION TABLE
Inputs ODxSEL_1 0 0 1 1 ODxSEL_0 0 1 0 1 Output Divider Value 32 (default) 8 4 1
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TABLE 3C. FREQUENCY FUNCTION TABLE
Input Frequency (MHz) 0.008 0.008 0.008 0.008 19.44 19.44 19.44 19.44 25 25 25 25 62.5 62.5 62.5 62.5 77.76 77.76 77.76 77.76 125 125 125 125 155.52 155.52 155.52 155.52 156.25 156.25 156.25 156.25 Pre-Divider Value 4 4 4 4 9720 9720 9720 9720 12500 12500 12500 12500 31250 31250 31250 31250 38880 38880 38880 38880 62500 62500 62500 62500 77760 77760 77760 77760 78125 78125 78125 78125 VCXO Frequency (MHz) 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 FemtoClock Feedback Divider Value 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Femtoclock VCO Frequency (MHz) 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 Output Divider Value 32 8 4 1 32 8 4 1 32 8 4 1 32 8 4 1 32 8 4 1 32 8 4 1 32 8 4 1 32 8 4 1 Output Frequency (MHz) 19.44 77.76 155.52 622.08 19.44 77.76 155.52 622.08 19.44 77.76 155.52 622.08 19.44 77.76 155.52 622.08 19.44 77.76 155.52 622.08 19.44 77.76 155.52 622.08 19.44 77.76 155.52 622.08 19.44 77.76 155.52 622.08
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PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Storage Temperature, TSTG 4.6V -0.5V to VCC + 0.5V 50mA 100mA -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause per manent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, JA 37C/W (0 mps)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V5%, VEE = 0V, TA = 0C TO 70C
Symbol VCC VCCA VCCO VCCX ICCA IEE ICCX Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Charge Pump Supply Voltage Analog Supply Current Output Supply Current Charge Pump Supply Current Test Conditions Minimum 3.135 VCC - 0.15 3.135 3.135 Typical 3.3 3.3 3.3 3.3 15 250 0.250 Maximum 3.465 VCC 3.465 3.465 Units V V V V mA mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V5%, VEE = 0V, TA = 0C TO 70C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage CLK_SEL, ODASEL_[0:1], Input High Current ODBSEL_[0:1] PDSEL[0:2] CLK_SEL, ODASEL_[0:1], Input Low Current ODBSEL_[0:1] PDSEL[0:2] Test Conditions Minimum 2 -0.3 VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 Typical Maximum VCC + 0.3 0.8 150 5 Units V V A A A A
IIL
NOTE 1: Outputs terminated with 50 to VCCO/2.
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V5%, VEE = 0V, TA = 0C TO 70C
Symbol IIH IIL VPP VCMR Parameter Input High Current Input Low Current CLK0/nCLK0, CLK1/nCLK1 CLK0, CLK1 nCLK0, nCLK1 Test Conditions VIN = VCC = 3.465V VIN = 0V, VCC = 3.465V VIN = 0V, VCC = 3.465V -5 -150 0.15 VEE + 0.5 1.3 VCC - 0.85 Minimum Typical Maximum 150 Units A A A V V
Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2
NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLKx, nCLKx is VCC + 0.3V.
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PRELIMINARY
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V5%, VEE = 0V, TA = 0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 0.9 VCCO - 1.7 1. 0 Units V V V
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V5%, VEE = 0V, TA = 0C TO 70C
Symbol Parameter fIN fOUT Input Frequency Output Frequency RMS Phase Jitter (Random); NOTE 1 Cycle-to-Cycle Jitter; NOTE 2, 3 Period Jitter; NOTE 4 Output Skew; NOTE 3, 5 Output Duty Cycle Output Rise/Fall Time 20% to 80% 155.52MHz fOUT, 19.44MHz crystal, Integration Range: 12kHz - 20MHz Test Conditions Minimum Typical Maximum Units 0.008 19.44 1.16 50 5 50 50 600 156.25 622.08 MHz MHz ps ps ps ps % ps ms
tjit(O) tjit(cc) tjit(per) tsk(o)
odc t R / tF
PLL Lock Time 100 tLOCK NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: Outputs terminated with 50 to VCCO - 2V. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Jitter performance using crystal inputs. NOTE 5: Defined as skew between outputs at the same supply voltage and with equal load condtions. Measured at the output differential cross points.
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PRELIMINARY
TYPICAL PHASE NOISE AT 155.52MHZ
SONET Filter
NOISE POWER dBc Hz
155.52MHz
RMS Phase Jitter (Random) 12kHz to 20MHz = 1.16ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding a SONET Filter to raw data OFFSET FREQUENCY (HZ)
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PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
2V 2V
VCC
VCC, VCCO, VCCX
Qx
SCOPE
VCCA
nCLK0, nCLK1
V
PP
Cross Points
V
CMR
LVPECL
nQx VEE
CLK0, CLK1
VEE
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
nQA, nQB QA, QB
tcycle n
DIFFERENTIAL INPUT LEVEL
nFOUTx FOUTx
tjit(cc) = tcycle n - tcycle n+1 1000 Cycles
CYCLE-TO-CYCLE JITTER
Phase Noise Plot
Noise Power
f1
Offset Frequency
RMS Jitter = Area Under the Masked Phase Noise Plot
PHASE JITTER
nQA, nQB QA, QB
t PW
t
PERIOD
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD
IDT TM / ICSTM VCXO JITTER ATTENUATOR/MULTIPLIER
tcycle n+1
nFOUTy FOUTy
tsk(o)
OUTPUT SKEW
VOH VREF
Phase Noise Mask
1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10-7)% of all measurements
VOL
f2
Reference Point
(Trigger Edge)
Histogram
Mean Period
(First edge after trigger)
PERIOD JITTER
nQA, nQB 80% 80% VSW I N G QA, QB 20% tR tF 20%
x 100%
OUTPUT RISE/FALL TIME
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PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS813322-02 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCX, VCCA, and VCCO should be individually connected to the power supply plane through vias, and 0.01F bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional10 resistor along with a 10F bypass capacitor be connected to the VCCA pin.
3.3V VCC .01F VCCA .01F 10 F 10
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC= 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input
CLKx
V_REF
nCLKx
C1 0.1u
R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
CLK/nCLK INPUTS For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVPECL OUTPUTS All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50 FOUT FIN
125 Zo = 50 FOUT
125
Zo = 50 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FIN
Zo = 50 84 84
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
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VFQFN EPAD THERMAL RELEASE PATH
In order to maximize both the removal of heat from the package and the electrical performance, a land patter n must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 4. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as "heat pipes". The number of vias (i.e. "heat pipes") are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor's Thermally/ Electrically Enhance Leadfame Base Package, Amkor Technology.
PIN
SOLDER
EXPOSED HEAT SLUG
SOLDER
PIN
PIN PAD
GROUND PLANE THERMAL VIA
LAND PATTERN (GROUND PAD)
PIN PAD
FIGURE 4. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH -SIDE VIEW (DRAWING NOT TO SCALE)
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SCHEMATIC EXAMPLE
Figure 5 shows an example of the ICS813322-02 application schematic. In this example, the device is operated at VCC = VCCX = VCCO = 3.3V. The decoupling capacitors should be located as close as possible to the power pin. The input is driven by a 3.3V
VC C R1 125 R2 125
LVPECL driver. An optional 3-pole filter can also be used for additional spur reduction. It is recommended that the loop filter components be laid out for the 3-pole option. This will also allow the 2-pole filter to be used.
Zo = 50
CLK1 nCLK1
Logic Control Input Examples
VCC
Zo = 50 VC C LVPECL Driv er R5 125 R6 125 R3 84 R4 84
Set Logic Input to '1'
RU1 1K
VCC
Set Logic Input to '0'
R U2 N ot Install
To Logic Input pins
Zo = 50 CLK0 nC LK0 Zo = 50 R7 84 LVPECL Driv er R8 85 C1 SP X1 XTAL_IN VCC C2 SP R 12 C5 0.01u 10 VC CX CLK0 nCLK0 VCC XTAL_OUT RD1 Not Install R D2 1K
To Logic Input pins
3.3V
R10 133 Zo = 50 Ohm C4 0.1u VC CO
R11 133
+
32 31 30 29 28 27 26 25
C6 10u U1
Zo = 50 Ohm 0.1u C7 R 13 82.5 VEE nQB QB VC CO nQA QA VEE ODASEL_0 24 23 22 21 20 19 18 17 nQA QA nQB QB ODASEL_0
-
LF Rs TBDk Cs TBDuF
LF 1 2 3 4 5 6 7 8
VCCX XTAL_IN XTAL_OUT CLK0 nCLK0 VCC CLK1 nCLK1
2-pole loop filter for Mid Bandwidth setting
R14 82.5
Cp TBD uF
VC C CLK_SEL
LF1 LF0 ISET VEE CLK_SEL VC C nc VEE PDSEL_2 PDSEL_1 PDSEL_0 VCC VCCA ODBSEL_1 ODBSEL_0 ODASEL_1
VCC = VCCX = VCCO= 3.3V
C8 0.1u
R15 2.21K
Zo = 50 Ohm + Zo = 50 Ohm -
3-pole loop filter example - (optional)
R9 LF Rs TBD k Cs TBD uF Cp TBDuF TBD k C3 TBDpF LF
IC S813322-02
ODBSEL_1 ODBSEL_0 ODASEL_1
PDSEL_2 PDSEL_1 PDSEL_0
9 10 11 12 13 14 15 16
R16 50
R17 50
VC C
R19 VC CA C9 0.1u C 10 0.01u C11 10u 10 VCC
Optional Y-Termination
R18 50
FIGURE 5. ICS813322-02 SCHEMATIC LAYOUT
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VCXO-PLL EXTERNAL COMPONENTS
Choosing the correct external components and having a proper printed circuit board (PCB) layout is a key task for quality operation of the VCXO-PLL. In choosing a crystal, special precaution must be taken with the package and load capacitance (CL). In addition, frequency, accuracy and temperature range must also be considered. Since the pulling range of a crystal also varies with the package, it is recommended that a metal-canned package like HC49 be used. Generally, a metal-canned package has a larger pulling range than a surface mounted device (SMD). For crystal selection information, refer to the VCXO Crystal Selection Application Note. the crystal specification. In either case, the absolute tuning range is reduced. The correct value of C L is dependant on the characteristics of the VCXO. The recommended CL in the Crystal Parameter Table balances the tuning range by centering the tuning curve. The VCXO-PLL Loop Bandwidth Selection Table shows RS, CS and CP values for recommended high, mid and low loop bandwidth configurations. The device has been characterized using these parameters. For other configurations, refer to the Loop Filter Component Selection for VCXO Based PLLs Application Note. The crystal and external loop filter components should be kept as close as possible to the device. Loop filter and crystal traces should be kept short and separated from each other. Other signal traces should be kept separate and not r un under neath the device, loop filter or crystal components.
LF0 LF1 ISET
The crystal's load capacitance CL characteristic determines its resonating frequency and is closely related to the VCXO tuning range. The total external capacitance seen by the crystal when installed on a board is the sum of the stray board capacitance, IC package lead capacitance, internal varactor capacitance and any installed tuning capacitors (CTUNE).
If the crystal CL is greater than the total external capacitance, the VCXO will oscillate at a higher frequency than the crystal specification. If the crystal CL is lower than the total external capacitance, the VCXO will oscillate at a lower frequency than
RS
CP CS
RSET
XTAL_IN CTUNE 19.44MHz CTUNE XTAL_OUT
VCXO CHARACTERISTICS TABLE
Symbol kVCXO CV_LOW CV_HIGH Parameter VCXO Gain Low Varactor Capacitance High Varactor Capacitance Typical 6000 15.9 29.8 Unit Hz/V pF pF
VCXO-PLL LOOP BANDWIDTH SELECTION TABLE
Bandwidth 10Hz (Low) 80Hz (Mid) 240Hz (High) Crystal Frequency (MHz) 19.44MHz 19.44MHz 19.44MHz RS (k ) 800 540 1000 CS (F) 1.8 0.15 0.25 CP (F) 0.0034 0.0015 0.0008 RSET (k ) 8.5 2.3 2.1
CRYSTAL CHARACTERISTICS
Symbol fN fT fS CL CO CO /C1 ESR Parameter Mode of Operation Frequency Frequency Tolerance Frequency Stability Operating Temperature Range Load Capacitance Shunt Capacitance Pullability Ratio Equivalent Series Resistance Drive Level Aging @ 25C 0 10 4 22 0 24 0 20 1 3 per year mW ppm Minimum Typical 19.44 20 20 70 Maximum Units MHz ppm ppm C pF pF Fundamental
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS813322-02. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS813322-02 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 250mA = 866.25mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 866.25mW + 60mW = 926.25mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 37C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.926W * 37C/W = 104.2C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA FOR 32-LEAD VFQFN, FORCED CONVECTION
JA vs. 0 Air Flow (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 37.0C/W
1
32.4C/W
2.5
29.0C/W
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT
AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination
voltage of V
CCO
- 2V. =V - 0.9V
*
For logic high, VOUT = V
OH_MAX
CCO_MAX
(VCCO_MAX - VOH_MAX) = 0.9V * For logic low, VOUT = VOL_MAX = VCCO_MAX - 1.7V (V
CCO_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 0.9V)/50] * 0.9V = 19.8mW ))/R ] * (V
L
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
32 LEAD VFQFN
JA vs. 0 Air Flow (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 37.0C/W
1
32.4C/W
2.5
29.0C/W
TRANSISTOR COUNT
The transistor count for ICS813322-02 is: 6331
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PACKAGE OUTLINE AND DIMENSIONS - K SUFFIX FOR 32 LEAD VFQFN
NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of
this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 8 below.
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS (VHHD -2/ -4) SYMBOL N A A1 A3 b e ND NE D, E D2, E2 L 3.0 0.30 0.18 0.50 BASIC 8 8 5.0 3.3 0.50 0.80 0 0.25 Reference 0.30 Minimum 32 1.0 0.05 Maximum
Reference Document: JEDEC Publication 95, MO-220
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TABLE 9. ORDERING INFORMATION
Part/Order Number 813322BK-02 813322BK-02T 813322BK-02LF 813322BK-02LFT Marking ICS13322B02 ICS13322B02 ICS3322B02L ICS3322B02L Package 32 Lead VFQFN 32 Lead VFQFN 32 Lead "Lead-Free" VFQFN 32 Lead "Lead-Free" VFQFN Shipping Packaging tray 2500 tape & reel tray 2500 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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(c) 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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